Curriculum Vitæ
Education
- PhD (Control Theory), UC Santa Barbara, 2028 (Expected)
- Stochastic Approximation of Hybrid Systems
- MS (ECE), UC Santa Barbara, 03/2025
- Coursework: Linear Systems, Nonlinear Control, Hybrid Systems, Stochastic Processes, Network Systems, Numerical Methods, Koopman Operator Theory, Estimation Theory
- Overall GPA: 4.00/4.00
- B.S. (Electrical Engineering), UC Santa Barbara, 06/2023
- Coursework: Continuous & Digital Control Systems, Kalman-Filtering & Optimal Estimation, RF Electronics, Circuit Design/Analysis, Digital Signal Processing, IC Fabrication, Electromagnetic/TL Theory, Machine Learning
- Overall GPA: 3.96/4.00
Work Experience
- Summer 2025: Toyon Research Corporation (Antenna & RF Systems Intern)
- Developed MATLAB code for satellite Doppler tracking.
- Generated C++ code using MATLAB Coder for real-time implementation on ROS.
- Summer 2024: ASML (Controls Research Intern)
- Designed an MPC cascade control design for regulating EUV dose in the ASML EXE5200 High-NA photolithography machine. Developed a linear optimal control formulation to inform the MPC cost function and constraint design.
- Analyzed the performance and robustness of the controller through statistical methods and ASML-specific KPIs.
- Conducted a feasibility study of a fixed-point FPGA implementation of the design.
- Summer 2023: SpaceX - Starlink (Associate Engineer - Postgrad)
- Designed, laid out, released, and programmed a daughter-board PCBA for a Raspberry Pi 4 to act as a connectivity tester for Ethernet links between boards in the Starlink satellite, functioning up to datarates of 25Gb/s. Developed for integration teams at Starlink manufacturing and launch facilities to reduce time spent debugging connectivity issues.
- Aided in debugging of on-orbit hardware failures and bring up of in-development PCBAs for next-gen satellites
- Wrote Python code to interface with the SpaceX telemetry API and diagnose on-orbit satellite hardware failures.
- Summer 2022: ASML (FPGA Engineering Intern)
- Developed hardware/firmware testbench plans for an FPGA-based DAQ module. Produced documentation, block diagrams, and proposals for test procedures of the testbench.
- Worked on a VHDL & SIMULINK HDL Coder based filter in parallel with main task. Developed from ground up through to implementation on an FPGA dev-board.
- Gained experience in programming VHDL, writing test-benches, Xilinx Vivado synthesis tools and IP cores, Modelsim, Makefiles/Buildfile automation, and FPGA verification.
- Summer 2021: ASML (Analog Electrical Engineering Intern)
- Worked to develop a differential block pulse amplifier for use as a laboratory prototype. Constructed a differential combiner assembly to combine block pulse and sinusoidal signals for use in driving a piezo-electric transducer. Produced documentation, startup and use procedures, daily reports/presentations, and wiring schematics for all components in the system.
Skills
- Programming Languages: MATLAB, Python, C++, VHDL
- Programs & CAD Tools: MATLAB, SIMULINK, Linux, Xilinx Vivado, Microsoft Office Programs, Atlassian Tools
Awards
